1. Technical Field
The embodiments herein relate to a semiconductor memory apparatus, and, more particularly, to a receiver circuit.
2. Related Art
A conventional receiver circuit of a semiconductor memory apparatus receives data from an external system, buffers the data, and delivers the data to an internal circuit of the semiconductor memory apparatus.
As shown in FIG. 1, a conventional receiver circuit includes first to fourth sense amplifiers 11, 12, 13, and 14, and first to fourth latch units 21, 22, 23, and 24. The first sense amplifier 11 detects and amplifies a voltage level difference between first external data signal ‘Data+’ and second external data signal ‘Data−’ to generate first and second sense signals ‘SA_out1’ and ‘SA_outb1’. The first sense amplifier 11 operates in synchronization of a first clock signal ‘CLK1’. The first latch unit 21 generates first internal data signal ‘Data_int 1’ in response to the first and second sense signals ‘SA_out1’ and ‘SA_outb1’.
The second sense amplifier 12 detects and amplifies the voltage level difference between the first external data signal ‘Data+’ and the second external data signal ‘Data−’ to generate third and fourth sense signals ‘SA_out2’ and ‘SA_outb2’. The second sense amplifier 12 operates in synchronization of a second clock signal ‘CLK2’. The second latch unit 22 generates second internal data signal ‘Data_int 2’ in response to the third and fourth sense signals ‘SA_out2’ and ‘SA_outb2’.
The third sense amplifier 13 detects and amplifies the voltage level difference between the first external data signal ‘Data+’ and the second external data signal ‘Data−’ to generate fifth and sixth sense signals ‘SA_out3’ and SA_outb3. The third sense amplifier 13 operates in synchronization of a third clock signal ‘CLK3’. The third latch unit 23 generates second internal data signal ‘Data_int 3’ in response to the fifth and sixth sense signals ‘SA_out3’ and SA_outb3.
The fourth sense amplifier 14 detects and amplifies the voltage level difference between the first external data signal ‘Data+’ and the second external data signal ‘Data−’ to generate seventh and eighth sense signals ‘SA_out4’ and ‘SA_outb4’. The fourth sense amplifier 14 operates in synchronization of a fourth clock signal ‘CLK4’. The first to fourth clock signals ‘CLK1’ to ‘CLK4’ have a phase difference of 90°. The fourth latch unit 24 generates fourth internal data signal ‘Data_int 4’ in response to the seventh and eighth sense signals ‘SA_out4’ and ‘SA_outb4’.
The receiver circuit having the above structure can determine four data during one period of a clock signal. However, the first to fourth sense amplifiers 11, 12, 13, and 14 must detect and amplify the voltage difference of the first and second external data signals ‘Data+’ and ‘Data−’ during ¼ period of a clock signal.
As a data rate is gradually increased, a clock frequency is also increased. Accordingly, as the clock frequency is increased, the operational time of the sense amplifiers 11, 12, 13, and 14 constituting the typical receiver shown in FIG. 1 is reduced. Therefore, a technology of ensuring an operation margin of such a receiver is necessary. If the operation margin of the receiver is not ensured, then the receiver may operate erroneously.